The biggest source of difficulty in the design of integrated circuits can be attributed directly or indirectly to sheer complexity. Complexity in this instance takes the form of the minute considerations which need to be made concerning timing in a circuit consisting of many thousands of transistors. In the process of continuous adaptation, much of this difficulty has been overcome - for present day requirements. Intelligent Logic provides the engineer with the chance to become acquainted with methods which do not depend on timing. These will increasingly be used for the more complex circuit designs of the future.
Designs using Intelligent Logic are comprised of modules each of which has the quality of speed independence (i.e. timing independence) which is imparted to the whole circuit. Each circuit module can complete its operation only after the data it receives is itself in a completed (defined) state. Some time after this its outputs, which are inputs to the next circuit modules, also become defined. In this way, a wave of completed module operations travels through the circuit. Eventually all the modules which take part in a given function will have completed their operations, the function itself will have been performed and output data from the circuit will be ready to be used externally.
Having been signalled operation complete, the external circuitry may then require another operation to be performed by the circuit. However before this can be achieved, the circuit must be reset to a neutral condition - the undefined state - which can be used to judge when the next operation is complete. This is effected by de-selecting the circuit. The same control circuitry as is used to show operation complete produces the 'ready' signal which indicates the circuit can be used again.
The next function is started with input signals to the circuit being in a defined condition - possibly as the result of a 'select' signal. Operation complete is signalled either by the state of the output signals or in a signal which is derived from the output signals.
Intelligent Logic provides prototype circuit elements in the form of macros held in a library. This is a library to which the engineer can and will contribute further prototypes; the means for doing this are provided. Complete designs are also available. These can be used by the engineer for reference and in particular by guided procedures which are used when the engineer wishes to make his own entries.
The process is self-educational. For example, the engineer can find out which macro was used to produce a given line of source using the pointer device to initiate a search for the icon. Having found the icon the engineer can then immediately proceed to build another similar line of source code. This is done mostly automatically requiring the engineer merely to give his own names to signals involved. Being checked against a model, the engineer will only be able to enter signals which are similar to those used in the model.
The engineer can select a macro through its icon and find where it has been used in a sample design. He can also call up associated information in the form of circuit diagrams and text - through the pointer device.